High Radix On-Chip Networks at Incremental Reconfiguration Cost

Networks-on-chip (NoCs) have become increasingly widespread due to the extensive integration of components in modern chip multi-processor (CMP) and SoC designs. A fundamental tradeoff in NoC design is the radix of its constituent routers. While high radix routers enable a richly connected and low diameter network, low radix routers provide simple and low power designs. In this work, we present HiROIC, a solution that provides high-radix like performance at a cost similar to a low-radix network. HiROIC leverages the irregularity in runtime communication patterns to provide short low-latency paths between frequently communicating nodes, while infrequently communicating pairs take longer paths. HiROIC deploys more links at a router than ports, binding ports to links at runtime depending on the traffic demands. Our experiments on a 64-node CMP, running multi-programmed workloads, show that HiROIC reduces average network latency by 19% over an areaand powercomparable mesh NoC.